August 30th, 2005

8.30 - 9.00
(Main Entrance)
Tutorial Day Registration
9.00 - 12.30
(Room B006)
Digital System Clocking: High-Performance and Low-Power Aspects
12.30 - 14.00Lunch
14.00 - 17.00
(Room B006)
System-Level Performance Analysis

Registration for the DSD Tutorial Day.

Digital System Clocking: High-Performance and Low-Power Aspects

Vojin G. Oklobdzija, University of California, Davis
Vladimir M. Stojanovic, MIT
Dejan M. Markovic University of California, Berkeley
Nikola M. Nedovic, Fujitsu America Laboratories

This tutorial provides up-to-date information on the most recent advances in the area of Digital System Clocking that has become one of the most important topics in the field of digital system design due to its high relevance to both High-Performance and Low-Power design.

1. Introduction
2. Theory of Clocked Storage Elements
3. Timing and Energy Parameters
4. Pipelining and Timing Analysis
5. High-Performance System Issues
6. Low-Energy System Issues
7. Simulation Techniques
8. State-of-the-Art Clocked Storage Elements in CMOS Technology
9. Microprocessor Examples

System-Level Performance Analysis

Piet van der Putten, Bart Theelen and Jeroen Voeten
Eindhoven University of Technology, The Netherlands

This tutorial presents a system-level methodology for predicting the performance of industrial-sized embedded systems. Starting from UML specification, the methodology derives formal executable performance models expressed in POOSL. These models are transformed into Markov chains to support both analytical and simulation-based performance evaluation. After presenting the theoretical background of the methodology, participants are invited to experiment with the supporting tools through a modest case study. This research was supported by the Dutch Program for Research on Embedded Systems and Software (PROGRESS).