Tuesday, August 30th
8:30-17:00
(Room B006)
DSD Tutorial Day
Wednesday, August 31st
8:30-9:30
(Main entrance)
Registration
9:30-10:00
(Auditório)
Opening Session
Keynote Speech I
Chair: Stefan Biffl
10:00-11:00
(Auditório)
Software Process Improvement Considered Obsolete: A Transition from Improvement-in-the-Large to Improvement-in-the-Small
Pekka Abrahamsson
11:00-11:30
(Room I-105)
Coffee Break
Keynote Speech II
Chair: A. Nunez
11:30-12:30
(Auditório)
Multi-media Applications and Imprecise Computation
Melvin A. Breuer
12:30-14:00
(Cantina)
Lunch
S1 — SS2: Dependability and Testing of Digital Systems, Part 1
Chair: H. Kubatova
14:00-15:00
(Room B010)
Bist Technique for GALS Systems
Milos Krstic, Eckhard Grass
Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming
Tun Li, Dan Zhu, Yang Guo, SiKun Li
S2 — System Synthesis, Part 1. Power Driven System Synthesis
Chair: L. Fanucci
14:00-15:00
(Room B013)
An Innovative MDA Methodology for Embedded Real-time System
A. Cuccuru, R. De Simone, T. Saunier, G. Siegel, Y. Sorel
Power-Composition Profile Driven Co-Synthesis with Power Management Selection for Dynamic and Leakage Energy Reduction
Dong Wu, Bashir M Al-Hashimi, Marcus Schmitz, Petru Eles
S3 — Circuit Synthesis, Part 1. Arithmetic
Chair: T. Sasao
14:00-15:00
(Room B011)
A Low-Power FIR Filter Using Combined Residue and Radix-2 Signed-Digit Representation
Andreas Lindahl, Lars Bengtsson
Approximating Trigonometric Functions with the Laws of Sines and Cosines using the Logarithmic Number System
Mark G Arnold
15:00-15:30
(Room I-105)
Coffee Break
S4 — SS2: Dependability and Testing of Digital Systems, Part 2
Chair: H. Kubatova
15:30-17:10
(Room B010)
Improvement of the Fault Coverage of the Pseudo-Random Phase in Column Matching BIST
Petr Fiser, Hana Kubatova
Characterization of Wavelet-based Image Coding Systems for Algorithmic Fault Detection
Lucía Costas Perez, Juan J. Rodríguez-Andina
Improved Fault Emulation for Synchronous Sequential Circuits
J. Raik, P. Ellervee, V. Tihhomirov, R. Ubar
Defect-Oriented Test-and Layout-Generation for Standard-Cell ASIC Designs
J. Sudbrock, J. Raik, R. Ubar, W. Kuzmicz, W. Pleskacz
Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
S5 — System Synthesis, Part 2. Component Based System Synthesis
Chair: K. Waldschmidt
15:30-17:00
(Room B013)
Hardware Design Based on Virtual Component Synthesis
A. Fouilliart, N. Abdelli, E. Casseau, B. Le Gall, Ch. Jego, N. Heno
High-Level Synthesis for DVB-DSNG Modem in an Optimized Latency Insensitive System Context
N. Abdelli, P. Bomel, P. Kajfasz, E. Martin, E. Boutillon, A. Fouilliart
Embedded Object Architecture
Tero Vallius, Juha Röning
An Effective Framework for Enabling the Reuse of External Soft IP
Soujanna Sarkar, Subash Chandar G.
S6 — Circuit Synthesis, Part 2. Logic Synthesis
Chair: T. Luba
15:30-16:40
(Room B011)
A Novel Method of Two-stage Decomposition Dedicated for PAL-based CPLDs
Dariusz Kania, Józef Kulisz, Adam Milik
An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS
Md.S. Shahriar, M.A.R. Mustafa, et al.
State Assignment for PAL-based CPLDs
Robert Czerwinski, Dariusz Kania
Coefficient Bit Reordering Method for Configurable FIR Filtering on Folded Bit-plane Array
Vladimir Ciric, Ivan Milentijevic
Automatic Design of Binary and Multiple-Valued Logic Gates on the RTD Series
Krzysztof S. Berezowski, Sarma B.K. Vrudhula
Poster Session 1
17:20-17:35
(Building B)

Papers [51, 60, 65, 13, 7, 23, 34]
18:00Cocktail/Reception
Thursday, September 1st
Keynote Speech III
Chair: Ivica Crnkovic
9:00-10:00
(Auditório)
Components in Product Lines — The Next Steps
Rob van Ommering
Keynote Speech IV
Chair: L. Jozwiak
10:00-11:00
(Auditório)
Design for Advanced Applications
Bernard Candaele
11:00-11:30
(Room I-105)
Coffee Break
Keynote Speech V
Chair: L. Jozwiak
11:30-12:30
(Auditório)
Wireless Sensor Systems - Constraints and Future Prospect
Dirk Timmermann
12:30-14:00
(Cantina)
Lunch
S7 — SS1: Wireless Sensor Systems, Part 1
Chair: Matthias Handy
14:00-15:15
(Room B010)
Design of Transport Triggered Architecture Processors for Wireless Encryption
P. Hämäläinen, J. Heikkinen, M. Hännikäinen, T. Hämäläinen
Mixed Signal CMOS Circuits for Ad-Hoc Networks (Invited paper)
C. Siu, K. Iniewski, F. Nabky, M. El-Gamal, K. Townsend, J. Haslett
Co-simulation of Wireless Local Area Network Terminals with Protocol Software Implemented in SDL
Petri Kukkala, Marko Hännikäinen, Timo D. Hämäläinen
Optimization of Electronic Power Consumption in Wireless Sensor Nodes
Y. Manoli, S.K. Ramachandran, S.K. Jayapal, R. Bhutada, R. Huang
Vital Signs Remote Management System for PDA
Danielly Cruz, Edna Barros
S8 — Verification Techniques
Chair: S. Ruelke
14:00-15:10
(Room B013)
MA2TG: A Functional Test Program Generator for Microprocessor Verification
Tun Li, Dan Zhu, Yang Guo, SiKun Li
A Processor for Testing Mixed-signal Cores in System-on-Chip
F. Duarte, J. Machado Silva, José C. Alves, J. Silva
Functional Test Generation Remote Tool
E. Bareisa, V. Jusas, K. Motiejunas, R. Seinauskas
Validation of Embedded Systems using Formal Method aided Simulation
Daniel Karlsson, Petru Eles, Zebo Peng
S9 — Application Specific Architectures, Part 1
Chair: J. Sosnowski
14:00-15:20
(Room B011)
VLSI Design of a High-Throughput Multi-Rate Decoder for Structured LDPC Codes
M. Rovini, Nicola E. L'Insalata, F. Rossi, Luca Fanucci
A FPGA Based Design of a Multiplierless and Fully Pipelined JPEG Compressor
L.V. Agostini, R.E. Carvalho Porto, I. Saraiva Silva, S. Bampi
Reconfigurable Parallel Approximate String Matching on FPGAs
Jin Hwan Park
Efficient MLP Digital Implementation on FPGA
S. Vitabile, V. Conti, F. Gennaro, F. Sorbello
Designing a Binary Neural Network Co-processor
Michael Freeman, Jim Austin
Efficient Host-Independent Coprocessor Architecture for Speech Coding Algorithms
H. Safizadeh, H. Noori, M. Sedighi, A. Jahanian, N. Zolfaghari
Massively Parallel Hardware Architecture for Genetic Algorithms
Nadia Nedjah, Luiza de Macedo Mourelle
Implementation of a Block Based Neural Branch Predictor
Oswaldo Cadenas, Graham Megson, Daniel Jones
PRUS - Processor Network for Digital Circuit Implementation
S. Hyduke, V. Hahanov, V. Obrizan, O. Guz
Capturing Processor Architectures from Protocol Processing Applications: a Case Study
Seppo Virtanen, Jani Paakkulainen, Tero Nurmi
Yield-aware Floorplanning
Zhaojun Wo, Israel Koren, Maciej Ciesielski
Poster Session 2
15:30-16:00
(Building B)

Papers [59, 73, 77, 109, 11, 37, 115, 74, 98, 111, 47, 80, 57, 122, 55, 14, 83]
15:30-16:00
(Room I-105)
Coffee Break
S10 — SS1: Wireless Sensor Systems, Part 2
Chair: Matthias Handy
16:00-17:30
(Room B010)
Design of a Development Platform for HW/SW Codesign of Wireless Integrated Sensor Nodes
K. Virk, M. Leopold, A. Vad Lorentzen, M. Hansen, P. Bonnet, J. Madsen
An Efficient MAC Protocol for Sensor Network Considering Energy Consumption and Information Retrieval
Yashar Ghiassi, Mohammad Mehdi Mansouri
Wireless Sensor Network Implementation for Industrial Linear Position Metering
Mikko Kohvakka, Marko Hännikäinen, Timo D. Hämäläinen
S11 — Verification Techniques, Part 2
Chair: Carlos Beltran
16:00-17:30
(Room B013)
MemBIST Applet for Learning Principles of Memory Testing and Generating a BIST Structure
Maria Fischerova, Martin Simlastik
High-Level Modelling and Detection of the Faulty Behaviour of VOQ Switches under Balanced Traffic
Miguel Pereira-Varela, Enrique Soto-Campos, Juan J. Rodriguez
Delay Testability Properties of Circuits Realizing Threshold Functions and Symmetric Functions
Piotr Patronik
S12 — Application Specific Architectures, Part 2
Chair: F. Leporati
16:00-17:30
(Room B011)
A New Architecture for Fast Arithmetic Coding in H.264 Advanced Video Coder
Roberto R. Osorio, Javier D. Bruguera
Exploring Graphics Processor Performance for General Purpose Applications
Pedro Trancoso, Maria Charalambous
Hardware-Based Implementation of the Common Approximate Substring Algorithm
Kenneth B. Kent, Sharon Van Schaick, J.E. Rice, P.A. Evan
20:00Conference Dinner
Friday, September 2nd
S13 — System Synthesis, Part 3. High Level Language based System Synthesis
Chair: J. Carlos Alves
9:00-10:25
(Room B010)
Cost-effective VLSI Design of Non Linear Image Processing Filters
S. Saponara, M. Cassiano, S. Marsi, R. Coen, L. Fanucci
Java to Hardware Compilation for non Data Flow Applications
Per Andersson, Krzysztof Kuchcinski
Formal Communication Semantics of SysetmC {FL}
K.L. Man
A high-level Tool for the Design of Custom Image Processing Systems
Sérgio Martins, José C. Alves
Processing of Streams on Multiprocessor Architecture
Nikolay Kavaldjiev, Gerard J.M. Smit, Pierre G. Jansen
S14 — Reconfigurable Systems, Part 1
Chair: A. Nunez
9:00-10:25
(Room B013)
A Constraints Programming Approach for Fabric Cell Synthesis
C. Wolinski, K. Kuchcinski
SystemC-based Design Methodology for Reconfigurable System-on-Chip
Yang Qu, Kari Tiensyrjä, Juha-Pekka Soininen
Reducing Inter-configuration Memory Usage and Performance Improvement in Reconfigurable Computing Systems
Farhad Mehdipour, Morteza Saheb Zamani, Mehdi Sedighi
An Adaptive On-line HW/SW Partitioning for Soft Real Time Reconfigurable Systems
G. Fakhreddine, A. Michel, A. Mohamed, B. Jemaa Maher
Using a Tightly-coupled Pipeline in Dynamically Reconfigurable Platform FPGAs
Miguel L. Silva, João Canas Ferreira
S15 — Data Management in SoC, Part 1
Chair: J.S. Matos
9:00-10:30
(Room B011)
Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-chip
Stuijk, Geilen, Basten, Mesman
An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures
F. Alexander R. Velez, M.S. Martin, M.F. Centeno, N. Bagherzadeh
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng
Poster Session 3
10:30-11:00
(Building B)

Papers [68, 71, 113, 72]
10:30-11:00
(Room I-105)
Coffee Break
Keynote Speech VI
Chair: Ivica Crnkovic
11:00-12:00
(Auditório)
UML and Components for System Modelling
François Terrier
Keynote Speech VII
Chair: K. Kuchcinski
12:00-13:00
(Auditório)
Networks on Chip
Hannu Tenhunen
13:00-14:30
(Cantina)
Lunch
S16 — SS3: Remote Educational Tools for Design and Testing, Part 1
Chair: R. Ubar
14:30-16:00
(Room B010)
An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform
Jaan Raik, Raimund Ubar
Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies
Josef Strnadel, Zdenek Kotasek
Remote Path Delay Fault Simulation
Øystein Gjermundnes, Einar J. Aas
Internet-based IC Technology Design and Simulation
V. Nelayev, V. Stempitsky, K. Kudin
S17 — Circuit Synthesis, Part 3. Advanced Logic Synthesis
Chair: J. Canas Ferreira
14:30-16:30
(Room B013)
Decomposition of Multi-Output Functions for CPLDs
Dariusz Kania, Jozef Kulisz
High-quality Sub-function Construction in the Information-driven Circuit Synthesis with Gates
Lech Jó Wiak, Szymon Biegaski
Efficient Implementation of Digital Filters with Use of Advanced Synthesis Methods Targeted FPGA Architectures
M. Rawski, P. Tomaszewicz, H. Selvaraj, T. Luba
On LUT Cascade Realizations of FIR Filters
Tsutomu Sasao, Yukihiro Iguchi, Takahiro Suzuki
S18 — Performance Optimization: Architecture and Tools, Part 1
Chair: K. Kuchcinski
14:30-16:00
(Room B011)
Run-time Adaptive Resource Allocation and Balancing on Nanoprocessors Arrays
Danilo Pani, Giuseppe Passino, Luigi Raffo
ARPA - A Technology Independent and Synthetizable System-on-Chip Model for Real-Time Applications
A.S.R. Oliveira, V.A. Sklyarov, A.B. Ferrari
Dynamic Split: Flexible Border Between Instruction and Data Cache
Pedro Trancoso
Work in Progress I
14:30-16:00
(Room B012)
Channel Widening Effect on the Effective Output Resistance of Deep-Submicron CMOS Line Driver and Its Application to Repeater Insertion
Andrea Pugliese, Franco Corapi, Gregorio Cappuccino
Modeling of Total Parameter Variations
Frank Sill, Dirk Timmermann
Enhancing the I-cache to Reduce the Power Consumption of Dynamic Branch Predictors
Colin Egan, Michael Hicks, Bruce Christianson, Patrick Quick
Achieving Optimal Circuit Performance of Synthesis For Large Bit Size Adders
Weng Fook Lee, Ali Yeon
Multiplier Execution Latency Reduction Using Variable Latency Pipeline
Tomáč Marek, Alois Pluháček
Design of Optimized Reconfigurable HW Tasks using Operation Graph Signatures
Maik Boden, Steffen Rülke, Jürgen Becker
Reconfigurable Duplex System Increasing Fault Tolerance for Circuits Based on FPGAs
Pavel Kubalík, Hana Kubátová
On the Petri Net Based Test Scheduling
Richard Ruzicka
Hardware Acceleration of Information Retrieval
Michael Freeman
16:30-17:00
(Room I-105)
Coffee Break
Work in Progress II
16:30-17:30
(Room B012)
Logarithmic Arithmetic for N-body Simulations
Mark Arnold, Philip Leong
Periodic Licensing of FPGA based Intellectual Property
Nathaniel Couture, Kenneth B. Kent
Packet Classification with Evolvable Hardware Hash Functions
Harald Widiger, Mathias Handy, Dirk Timmermann
Developing an Ubiquitous Computing Demonstrator
Michael Freeman, Chris Bailey
Efficient Data Feeding for Smart Vision System
G. Danese, M. Giachero, F. Leporati, N. D. Nazzicari, A. Sartori
Implementing the Styx Network Protocol in Hardware
Ameet Patil, Michael Freeman, Rui Gao, Chris Bailey